Analogue Core-Based Test-Pattern Generation*

– Core-based testing, which is described by the proposed IEEE standard P1500, is an effective test method for Systems-on-Chip (SOC) containing embedded cores. This test method is usable for all classes of digital cores and provides solutions that allow automatic identification and configuration of testability features in SOC containing embedded cores. In this moment, IEEE P1500 is restricted to digital ICs, but nowadays many SOC include also analog parts and there is no effective solution to test the embedded analog cores. In our work, we try to extend the ideas of IEEE P1500 for analog cores. First, a defect-oriented testing (DOT) approach is used for local testing of each stand-alone core. Then a concept of a structural test access mechanism for embedded cores is proposed to transport test stimuli from the IC inputs to the core under test and transport test response from core under test to the IC outputs, where DfT and mixed-signal test bus are used. As an example, the analog front-end of a system-on-chip including the new test hardware was evaluated by means of simulation. Keywords–– Analogue core-based testing, analogue structural testing, mixed-mode simulation